AMD Advances EPYC Roadmap with TSMC’s 2nm Production for Venice Processor

AMD has initiated production of its next-generation EPYC server processor, codenamed "Venice," leveraging TSMC's cutting-edge 2nm process technology. The rollout begins in Taiwan with planned expansion to TSMC's Arizona facility, marking a strategic push to meet escalating demand for high-performance computing in AI and cloud infrastructure.

The Venice chip represents AMD's first HPC CPU built on a 2nm node, promising significant gains in energy efficiency and computational power. Advanced packaging techniques like TSMC's SoIC-X and CoWoS-L further enhance performance, positioning AMD to challenge rivals in the hyperscale data center market.

While AMD shares dipped 0.7% to $444.46, the production ramp underscores the company's technological lead in semiconductor fabrication. The roadmap includes 6th-gen "Verano" processors optimized for AI workloads, reflecting the industry's pivot toward specialized computing architectures.